Mark Lord wrote:
Alan Cox wrote:
DMA alignment is host restriction so I think it belongs to ata_host if
we ever need it. Do you know of any controller which require such
thing? No need to add complexity when it's not necessary.
If we ever get the blasted inic162x working then that appears to have
some alignment limits. At least the docs say the DMA buffers must be quad
word aligned and sized (although it doesn't describe what occurs if the
total length of xfer disagrees with the buffers)
...
If it's an ADMA device, then they may support bits in the CPB
to direct what should happen for various overrun/underrun conditions.
Yeah most devices that are not strictly SFF (i.e. have a real register
space) are like that.
Jeff
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