Benjamin Herrenschmidt wrote:
Another thing about the PacDigi core: one has to be very careful
to avoid sequential accesses to sequential PCI locations when
programming the chip -- it cannot handle merged register writes.
So for any group of sequentially laid out registers, the code has
to ensure it never writes two adjacent registers in sequence..
Ugh ? Write combining isn't permitted on normal registers afaik...
Ben.
Byte merging can be done by the chipset on MMIO writes (merging multiple
8 or 16-bit writes into a single 32-bit cycle).
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