On Sat, Feb 02, 2008 at 12:35:30AM +0100, Bartlomiej Zolnierkiewicz wrote:
> > > Index: b/drivers/ide/arm/icside.c
> > > ===================================================================
> > > --- a/drivers/ide/arm/icside.c
> > > +++ b/drivers/ide/arm/icside.c
> > > @@ -459,11 +456,19 @@ icside_register_v5(struct icside_state *
> > >
> > > idx[0] = hwif->index;
> > >
> > > - ide_device_add(idx);
> > > + ide_device_add(idx, NULL);
> > >
> > > return 0;
> > > }
> > >
> > > +static const struct ide_port_info icside_v6_port_info __initdata = {
> > > + .host_flags = IDE_HFLAG_SERIALIZE |
> > > + IDE_HFLAG_NO_DMA | /* no SFF-style DMA */
> > > + IDE_HFLAG_NO_AUTOTUNE,
> > > + .mwdma_mask = ATA_MWDMA2,
> > > + .swdma_mask = ATA_SWDMA2,
> > > +};
> > > +
> >
> > Interesting... this driver's support for SWDMA0 is broken since the
> > cycle
> > should be 960 ns long, not 480, and SWDMA2 is underclocked using the same
> > cycle as SWDMA1, 480 ns...
>
> Added Russell to Cc:.
Underclocking the DMA is not a problem - if you look at the timing
diagrams and associated tables in the ATA specifications, you'll
find that they specify the *minimum* cycle timings.
However, you're correct that SWDMA0 is not able to be supported.
--
Russell King
Linux kernel 2.6 ARM Linux - http://www.arm.linux.org.uk/
maintainer of:
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