On Thu, Sep 11, 2025 at 04:51:24PM +0200, Alexander Wilhelm wrote: > On Thu, Sep 11, 2025 at 03:26:38PM +0100, Mark Brown wrote:
> > That sounds like the controller is configured in word mode and is > > bouncing chip select after every word it sends. The Freescale > > controllers are fond of implementing and using that, no idea about this > > specific one. I see there's some non-standard DT properties it has > > which look like they're related to chip select modes but no idea what > > they do. > Which DT properties are you referring to? I’ve only used the default ones > provided by the QorIQ DTS files in the kernel. The various "fsl," ones the driver reads. Though now I grep for docs they seem timing related and irrelevant :/ . You could also look at the datasheet and see if you can fix the configuration in the driver for this case, possibly there might be some performance overhead if it's possible. > > Can you not pinmux the signal from the SoC to a GPIO instead of the SPI > > controller? It's fairly common to do that since controllers often have > > regrettably limited or unhelpful chip select features so GPIOs are often > > the better choice. The controller does what it likes with the chip > > select signal but it's not actually connected to anything and we do > > everything in software. > The problem here is that RCW allows either both enabled SPI + CS or disabled > SPI > and CS-pins set to GPIO. Furthermore it is unfortunatelly connected, so I > cannot > simple cut the path on PCB and need a more complicated re-design of it. Oh, well - that's unfortunate pinmuxing. Glad to see innovation! > > I'd recommend contacting whoever looks after the relevant controller > > driver, though it looks rather abandoned TBH. > Hopefully, someone with experience in this kind of setup will respond via the > mailing list. I'd try to explicitly CC people in TBH.
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