> IIRC, the K6-2+ is really a K6-3 core with the on-chip L2 cache disabled
> because of defects.
My recollection (starting with the K6-3+ and then going to the K6-2+ - if
there are any errors, please correct me):
The K6-3+ is a K6-3 produced on a smaller process (180nm, as opposed to
the K6-3's 250nm (I think it was 250, anyway)). Some of these also have
PowerNow(tm), which is like Intel's SpeedStep(tm) but with a wider range of
speeds.
The K6-2+ is a K6-3+ with half of the on-chip L2 cache disabled.
Anyway, my previous email was describing the rationale that AMD used to
arrive at the K6-2+ name.
-Barry K. Nathan <[EMAIL PROTECTED]>
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