On Nov 3, 2015, at 3:43 PM, Guy Harris <g...@alum.mit.edu> wrote:
> To which particular PA-RISC processor are you referring? It might not be the
> same on all processors.
Chapter 3 "Addressing and Access Control" of PA-RISC 2.0 Architecture:
http://h21007.www2.hp.com/portal/download/files/unprot/parisc20/PA_3_addressing.pdf
says
A consistent software view of cache operation requires that
implementations never write a clean cache line back to memory. (A cache line
can be 16, 32, or 64 bytes in length.) Clean means “not stored into” as opposed
to “not changed”. Dirty means “stored into”. A cache line which was stored into
in such a way that it was unchanged is considered to be dirty.
so, architecturally, it can be 16, 32, or 64 bytes.
I'm not sure what
When Linux says 'line size' it generally means the cache ownership line
size: the minimum block the inter cpu coherence operates on. Most of the
architectural evidence for PA systems suggests that this is 16
from the mail message cited means when it speaks of architectural evidence; is
that line size different from the line size in the PA-RISC 2.0 Architecture
manual? That line size presumably isn't the burst size:
128 seems to be the cache burst fill size (the number of bytes that
will be pulled into the
cache by a usual operation touching any byte in the area).--
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