Remi Pommarel <r...@triplefau.lt> writes: > Some bcm2835 clocks used by hardware (like "PWM" or "H264") can have multiple > parents. These clocks divide the rate of one parent which can be selected by > setting the proper bits in their clock control register. > > Previously all these parents where handled by a mux clock. But a mux clock > cannot be used because updating clock control register to select parent needs > a > password to be xor'd with the parent index.
Good point. I previously was doing parent detection from muxes
manually, then simplified to using the generic mux later. I didn't have
any clocks I wanted to change mux on, so I missed this requirement.
It looks like there's not too much work to folding the muxing back into
the driver, so it seems like you have a good plan.
> -static long bcm2835_clock_round_rate(struct clk_hw *hw,
> - unsigned long rate,
> - unsigned long *parent_rate)
> -{
> - struct bcm2835_clock *clock = bcm2835_clock_from_hw(hw);
> - u32 div = bcm2835_clock_choose_div(hw, rate, *parent_rate);
> -
> - return bcm2835_clock_rate_from_divisor(clock, *parent_rate, div);
> -}
> -
> static unsigned long bcm2835_clock_get_rate(struct clk_hw *hw,
> unsigned long parent_rate)
> {
> @@ -1278,13 +1268,69 @@ static int bcm2835_clock_set_rate(struct clk_hw *hw,
> return 0;
> }
>
> +static int bcm2835_clock_determine_source(struct clk_hw *hw,
> + struct clk_rate_request *req)
> +{
> + struct clk_hw *parent, *best_parent = NULL;
> + struct clk_rate_request parent_req;
> + unsigned long prate, best_rate = ULONG_MAX;
> + size_t i;
> +
> + /*
> + * Select parent clock that has the closest but higher rate
> + */
> + for (i = 0; i < clk_hw_get_num_parents(hw); ++i) {
> + parent = clk_hw_get_parent_by_index(hw, i);
> + if (!parent)
> + continue;
> + parent_req = *req;
> + prate = clk_hw_get_rate(parent);
> + if (prate < best_rate && prate >= req->rate) {
> + best_parent = parent;
> + best_rate = prate;
> + }
> + }
> +
> + if (!best_parent)
> + return -EINVAL;
> +
> + req->best_parent_hw = best_parent;
> + req->best_parent_rate = best_rate;
> +
> + return 0;
> +}
It looks like you've dropped the use of the divisor off of the PLL
channel when setting a rate. That seems bad for all the other clocks in
the system, and a feature we couldn't lose.
Also, you're choosing the lowest but higher rate, while
mux_is_better_rate() chooses the highest but lower rate (which seems
much safer). What led to that choice?
Also, if we're going to have this function, I think it should be called
"bcm2835_clock_determine_rate" to match the method name.
The parent get/setting looks good, though.
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