On Mon, Nov 09, 2015 at 01:59:02PM -0600, gratian.cri...@ni.com wrote: > The Intel Xeon E5 processor family suffers from errata[1] BT81:
> +#ifdef CONFIG_X86_TSC > + /* > + * Xeon E5 BT81 errata: TSC is not affected by warm reset. > + * The TSC registers for CPUs other than CPU0 are not cleared by a warm > + * reset resulting in a constant offset error. > + */ > + if ((c->x86 == 6) && (c->x86_model == 0x3f)) > + set_cpu_bug(c, X86_BUG_TSC_OFFSET); > +#endif That's hardly a family, that's just one, Haswell server. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
