> On Wed, Nov 11, 2015 at 12:03:39PM +0530, Bharat Kumar Gogada wrote: > > Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP. > > > > Signed-off-by: Bharat Kumar Gogada <bhara...@xilinx.com> > > Signed-off-by: Ravi Kiran Gummaluri <rgum...@xilinx.com> > > I acked v7. Please add acks when sending a new version. Hi Rob, I'm sorry for not adding I forgot to do so, I will definitely add this in next patch.
Regards, Bharat Kumar Gogada > > Acked-by: Rob Herring <r...@kernel.org> -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
