On Thu, Dec 07, 2006 at 08:31:08PM +1100, Nick Piggin wrote: > Wrong. Your ll/sc implementation with cmpxchg is buggy. The cmpxchg > load_locked is not locked at all, and there can be interleaving writes > between the load and cmpxchg which do not cause the store_conditional > to fail. > > It might be reasonable to implement this watered down version, but: > don't some architectures have restrictions on what instructions can > be issued between the ll and the sc?
On MIPS the restriction is no loads or stores or sync instructions between ll/sc. Also there may be at most 2048 bytes between the address of the ll and sc instructions. Which means ll/sc sequences should better be written in assembler or gcc might do a bit too creative things ... Ralf - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/