On Fri, Dec 18, 2015 at 11:45:29AM -0600, Christoph Lameter wrote: > On Thu, 17 Dec 2015, Fenghua Yu wrote: > > > Intel Cache allocation support: > > > > Cache allocation patches adds a cgroup subsystem to support the new > > Cache Allocation feature found in future Intel Xeon Intel processors. > > Cache Allocation is a sub-feature with in Resource Director > > Technology(RDT) feature. Current patches support only L3 cache > > allocation. > > > > Cache Allocation provides a way for the Software (OS/VMM) to restrict > > cache allocation to a defined 'subset' of cache which may be overlapping > > with other 'subsets'. This feature is used when a thread is allocating > > a cache line ie when pulling new data into the cache. > > > > Threads are associated with a CLOS(Class of service). OS specifies the > > CLOS of a thread by writing the IA32_PQR_ASSOC MSR during context > > switch. The cache capacity associated with CLOS 'n' is specified by > > writing to the IA32_L3_MASK_n MSR. > > Could you also support another low level interface where a task (or > process) can set the CLOS id itself if it has CAP_SYS_NICE.
Hi Christoph, Do you have a proposal for an interface? > Plus some way > for the supervisor to directly control the IA32_L3_MASK_n MSR? What you mean supervisor? Hypervisor or root user? > Is there a way to see these values for debugging purposes? Yes, from userspace, wrmsr and rdmsr. > We tightly control processes and bind them to processors. cpusets are > often a too high level instrument at that level. -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
