On 01/30/2016 09:10 AM, Jonathan Cameron wrote:
On 25/01/16 17:29, Andrew F. Davis wrote:
+
+static int afe4403_read(struct afe4403_data *afe, unsigned int reg, u32 *val)
+{
+ u8 tx[4] ____cacheline_aligned = {AFE440X_CONTROL0, 0x0, 0x0,
+ AFE440X_CONTROL0_READ};
hmm. Can you do this on the stack? Don't think so but maybe I'm wrong..
The cachline aligned trick relies on the start of the allocation on the
heap being aligned and then pads to ensure that the element so tagged
is also aligned appropriately.
I am not sure ether, I think I borrowed this from some example that did
it like this, but I can't find it now. So, I'll change this to be safe.
+ u8 rx[3];
+ int ret;
Even if this were possible, ret is in the same cacheline as tx and rx so
chaos may well occur.
If you really want to avoid having allocations elsewhere, just use
spi_write_then_read(afe->spi, tx, 4, NULL, 0) and you should be fine
as spi_write_then_read uses safe bounce buffers.
spi_write_then_read performs a memcpy to the rx buffer, even though
the length is 0 I believe it is still technically undefined behavior,
but it doesn't seem to cause any issues with the current implementation
so I'll do this.
Thanks,
Andrew
