On Wed, 3 Feb 2016, Paul Burton wrote:
> diff --git a/arch/mips/kernel/perf_event_mipsxx.c
> b/arch/mips/kernel/perf_event_mipsxx.c
> index d7b8dd4..ae378d9 100644
> --- a/arch/mips/kernel/perf_event_mipsxx.c
> +++ b/arch/mips/kernel/perf_event_mipsxx.c
> @@ -1556,6 +1556,7 @@ static const struct mips_perf_event
> *mipsxx_pmu_map_raw_event(u64 config)
> #endif
> break;
> case CPU_P5600:
> + case CPU_P6600:
> case CPU_I6400:
> /* 8-bit event numbers */
> raw_id = config & 0x1ff;
> @@ -1718,6 +1719,11 @@ init_hw_perf_events(void)
> mipspmu.general_event_map = &mipsxxcore_event_map2;
> mipspmu.cache_event_map = &mipsxxcore_cache_map2;
> break;
> + case CPU_P6600:
> + mipspmu.name = "mips/P6600";
> + mipspmu.general_event_map = &mipsxxcore_event_map2;
> + mipspmu.cache_event_map = &mipsxxcore_cache_map2;
> + break;
> case CPU_I6400:
> mipspmu.name = "mips/I6400";
> mipspmu.general_event_map = &mipsxxcore_event_map2;
> diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c
> index 8489c88..d6e6cf7 100644
> --- a/arch/mips/kernel/spram.c
> +++ b/arch/mips/kernel/spram.c
> @@ -210,6 +210,7 @@ void spram_config(void)
> case CPU_P5600:
> case CPU_QEMU_GENERIC:
> case CPU_I6400:
> + case CPU_P6600:
> config0 = read_c0_config();
> /* FIXME: addresses are Malta specific */
> if (config0 & (1<<24)) {
Minor nit: you sometimes place the I6400 before and sometimes after the
P6600 -- would it make sense to keep the ordering consistent?
Maciej
