On Wed, Feb 10 2016 at 03:13 -0700, Mark Brown wrote:
On Tue, Feb 09, 2016 at 03:21:54PM -0700, Lina Iyer wrote:
On Tue, Feb 09 2016 at 06:13 -0700, Georgi Djakov wrote:
Please delete unneeded context from mails when replying. Doing this
makes it much easier to find your reply in the message, helping ensure
it won't be missed by people scrolling through the irrelevant quoted
material.
Sorry.
>+#define SPM_REG_STS_1 0x10
>+#define SPM_REG_VCTL 0x14
>+#define SPM_REG_PMIC_DATA_0 0x28
>+#define SPM_REG_PMIC_DATA_1 0x2c
>+#define SPM_REG_RST 0x30
These register offsets are SoC specific. You may want to follow the model
of drivers/soc/qcom/spm.c in getting register offsets.
While I see that you are only supporting APQ8064 with this patch, you
probably would want to think a bit far ahead. To support any other QCOM
SoC, you would need extensive changes.
This has already been applied. It's not immediately clear to me that
changes simply to move the registers around would be more extensive than
just adding fields to the driver data, is it more than just that?
The offsets are the simple part. On other QCOM SoCs the voltage is
regulated by the SAW attached to the L2 cache controller. They have a
single rail that supplies power to all the cores and the L2, with
ability to change the number of phases to match the load. This driver
supports 8064 which has individual CPU rails, while the rest of the QCOM
SoC's share a common rail design.
While the regulator changes are orthogonal between 8064 and the rest of
the QCOM SoC's, it might have been nicer to look ahead into other SoC's
that may share similar compatible (with a different version ofcourse),
for the design of this driver. That said, the functionality of the
driver seems like what is needed for 8064 and I wouldnt want to stop the
upstreaming process. It might need changes to abstract offsets,
identifying the SAW regulator that will change the voltage on that SoC
etc., in the future to support both class of SoCs.
Thanks,
Lina
