This patchset mainly provides necessary EDAC bits to decode errors occuring on Scalable MCA enabled processors and also updates AMD MCE driver to get correct MCx_MISC register address for upcoming processors. Patches 1 ans 2 are meant for the upcoming processors.
Patches 3 and 4 are either fixing or adding comments to help in understanding the code and do not introduce any functional changes. Patch 1: Updates to EDAC driver to decode the new error signatures Patch 2: Fix logic to get correct block address Patch 3: Fix deferred error comment Patch 4: Add comments to mce_amd.c to describe functionality Tested the patches for regressions on Fam15h, Fam10h systems and found none. Aravind Gopalakrishnan (4): EDAC, MCE, AMD: Enable error decoding of Scalable MCA errors x86/mce/AMD: Fix logic to obtain block address x86/mce: Clarify comments regarding deferred error x86/mce/AMD: Add comments for easier understanding arch/x86/include/asm/mce.h | 52 +++++- arch/x86/include/asm/msr-index.h | 6 + arch/x86/kernel/cpu/mcheck/mce_amd.c | 126 ++++++++++---- drivers/edac/mce_amd.c | 327 ++++++++++++++++++++++++++++++++++- 4 files changed, 480 insertions(+), 31 deletions(-) -- 2.7.0
