On Wed, Mar 23, 2016 at 6:01 PM, Alexander Stein <[email protected]> wrote:
> The interrupt for the corresponding pin is configured to trigger when the > pin state changes compared to a preconfigured state (Bit set in INTCON). > This state is set by setting/clearing the bit in DEFVAL. > In the interrupt handler we need also to check if the bit in INTCON is set > for level triggered interrupts. > > Signed-off-by: Alexander Stein <[email protected]> Patch applied. I'm a bit concerned that you now support both edge and level trigged IRQs but this driver is using handle_simple_irq() in the gpiochip_irqchip_add() call. I guess it "just works" because the hardware will latch the edge IRQ and clear it when reading the status register. I guess you have tested it with both edge and level IRQs? Yours, Linus Walleij
