On 04/08/2016 12:20 PM, Eric Anholt wrote:
Stephen Warren <swar...@wwwdotorg.org> writes:
On 04/04/2016 09:44 PM, Eric Anholt wrote:
dsb() requires an argument on arm64, so we needed to add "sy".
Instead, take this opportunity to switch to the same smp_wmb() call
that gic uses for its IPIs. This is a less strong barrier than we
were doing before (dmb(ishst) compared to dsb(sy)), but it seems to be
the correct one.
I assume all MMIO is part of the ish domain?
If so, the series,
Acked-by: Stephen Warren <swar...@wwwdotorg.org>
I don't know if this barrier implies ordering all the way out to AXI on
this HW, but I don't think that's a requirement of this function.
My understanding was that the barrier was explicitly to work around a
bug in the bus fabric of the SoC, and hence the barrier very much does
have to affect the transaction all the way out to AXI. Re-reading
BCM2835-ARM-Peripherals.pdf section 1.3 "Peripheral access precautions
for correct memory ordering" seems to confirm this.
