> > The overhead of timer interrupts at this low clockrate is significant > > so I recommend to minimize the timer interrupt rate as far as possible. > > This is really a tradeoff between latency and overhead and matters > > much less on hardcores which run at hundreds of MHz. For power sensitive > > applications lowering the interrupt rate can also help. And that's alredy > > pretty much what you need to know, that is a 10ms timer is fine. > > > > I have worked with FPGA Linux system which is reconfigurable > on-the-fly by the 200Mhz ARM9 CPU running Debian Linux, Altera Cyclone > II FPGA is included on my TS-7300 board. Advantage is, Altera FPGA and > a dedicated high-speed bus between the CPU and FPGA provides a good > design scope to provide many solutions.
What's your point here? A 200MHz hard ore won't see the issues under discussion. We're talking about systems where the CPU itself is "soft" and implemented in an FPGA. Regards, Kevin K. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/