This patch adds core dtsi file for Rockchip RK3399 SoCs.

The RK3399 has big/little architecture, which needs a separate
node for the PMU of each microarchitecture, for now it missing
the pmu node since the old one could not work well.

Marc is working on it with:
https://lkml.org/lkml/2016/4/11/182

and on the following branch:
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
irq/percpu-partition

And it has been tested on RK3399 evb and works well.

Tested-by: Brian Norris <briannor...@chromium.org>
Signed-off-by: Jianqun Xu <jay...@rock-chips.com>
---
changes in v3:
- tested irq/percpu-partition patches and worked well (huangtao)
- tested by Brian

changes in v2:
- remove rk808 since without i2c, which will upstream independently
- remove es8316 since without i2c, which will upstream independently
- fix codingstyle issues

 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1022 ++++++++++++++++++++++++++++++
 1 file changed, 1022 insertions(+)
 create mode 100644 arch/arm64/boot/dts/rockchip/rk3399.dtsi

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi 
b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
new file mode 100644
index 0000000..5a8a915
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -0,0 +1,1022 @@
+/*
+ * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/clock/rk3399-cru.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+
+/ {
+       compatible = "rockchip,rk3399";
+
+       interrupt-parent = <&gic>;
+       #address-cells = <2>;
+       #size-cells = <2>;
+
+       aliases {
+               serial0 = &uart0;
+               serial1 = &uart1;
+               serial2 = &uart2;
+               serial3 = &uart3;
+               serial4 = &uart4;
+       };
+
+       psci {
+               compatible = "arm,psci-1.0";
+               method = "smc";
+       };
+
+       cpus {
+               #address-cells = <2>;
+               #size-cells = <0>;
+
+               cpu-map {
+                       cluster0 {
+                               core0 {
+                                       cpu = <&cpu_l0>;
+                               };
+                               core1 {
+                                       cpu = <&cpu_l1>;
+                               };
+                               core2 {
+                                       cpu = <&cpu_l2>;
+                               };
+                               core3 {
+                                       cpu = <&cpu_l3>;
+                               };
+                       };
+
+                       cluster1 {
+                               core0 {
+                                       cpu = <&cpu_b0>;
+                               };
+                               core1 {
+                                       cpu = <&cpu_b1>;
+                               };
+                       };
+               };
+
+               cpu_l0: cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       reg = <0x0 0x0>;
+                       enable-method = "psci";
+                       #cooling-cells = <2>; /* min followed by max */
+                       clocks = <&cru ARMCLKL>;
+               };
+
+               cpu_l1: cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       reg = <0x0 0x1>;
+                       enable-method = "psci";
+                       clocks = <&cru ARMCLKL>;
+               };
+
+               cpu_l2: cpu@2 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       reg = <0x0 0x2>;
+                       enable-method = "psci";
+                       clocks = <&cru ARMCLKL>;
+               };
+
+               cpu_l3: cpu@3 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a53", "arm,armv8";
+                       reg = <0x0 0x3>;
+                       enable-method = "psci";
+                       clocks = <&cru ARMCLKL>;
+               };
+
+               cpu_b0: cpu@100 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a72", "arm,armv8";
+                       reg = <0x0 0x100>;
+                       enable-method = "psci";
+                       #cooling-cells = <2>; /* min followed by max */
+                       clocks = <&cru ARMCLKB>;
+               };
+
+               cpu_b1: cpu@101 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a72", "arm,armv8";
+                       reg = <0x0 0x101>;
+                       enable-method = "psci";
+                       clocks = <&cru ARMCLKB>;
+               };
+       };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+       };
+
+       xin24m: xin24m {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <24000000>;
+               clock-output-names = "xin24m";
+       };
+
+       amba {
+               compatible = "arm,amba-bus";
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+
+               dmac_bus: dma-controller@ff6d0000 {
+                       compatible = "arm,pl330", "arm,primecell";
+                       reg = <0x0 0xff6d0000 0x0 0x4000>;
+                       interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                       #dma-cells = <1>;
+                       clocks = <&cru ACLK_DMAC0_PERILP>;
+                       clock-names = "apb_pclk";
+               };
+
+               dmac_peri: dma-controller@ff6e0000 {
+                       compatible = "arm,pl330", "arm,primecell";
+                       reg = <0x0 0xff6e0000 0x0 0x4000>;
+                       interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                       #dma-cells = <1>;
+                       clocks = <&cru ACLK_DMAC1_PERILP>;
+                       clock-names = "apb_pclk";
+               };
+       };
+
+       sdio0: dwmmc@fe310000 {
+               compatible = "rockchip,rk3399-dw-mshc",
+                            "rockchip,rk3288-dw-mshc";
+               reg = <0x0 0xfe310000 0x0 0x4000>;
+               interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+               clock-freq-min-max = <400000 150000000>;
+               clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
+                        <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+               clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+               fifo-depth = <0x100>;
+               status = "disabled";
+       };
+
+       sdmmc: dwmmc@fe320000 {
+               compatible = "rockchip,rk3399-dw-mshc",
+                            "rockchip,rk3288-dw-mshc";
+               reg = <0x0 0xfe320000 0x0 0x4000>;
+               interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+               clock-freq-min-max = <400000 150000000>;
+               clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+                        <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+               clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+               fifo-depth = <0x100>;
+               status = "disabled";
+       };
+
+       sdhci: sdhci@fe330000 {
+               compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
+               reg = <0x0 0xfe330000 0x0 0x10000>;
+               interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
+               clock-names = "clk_xin", "clk_ahb";
+               status = "disabled";
+       };
+
+       usb_host0_ehci: usb@fe380000 {
+               compatible = "generic-ehci";
+               reg = <0x0 0xfe380000 0x0 0x20000>;
+               interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
+               clock-names = "hclk_host0", "hclk_host0_arb";
+               status = "disabled";
+       };
+
+       usb_host0_ohci: usb@fe3a0000 {
+               compatible = "generic-ohci";
+               reg = <0x0 0xfe3a0000 0x0 0x20000>;
+               interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
+               clock-names = "hclk_host0", "hclk_host0_arb";
+               status = "disabled";
+       };
+
+       usb_host1_ehci: usb@fe3c0000 {
+               compatible = "generic-ehci";
+               reg = <0x0 0xfe3c0000 0x0 0x20000>;
+               interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
+               clock-names = "hclk_host1", "hclk_host1_arb";
+               status = "disabled";
+       };
+
+       usb_host1_ohci: usb@fe3e0000 {
+               compatible = "generic-ohci";
+               reg = <0x0 0xfe3e0000 0x0 0x20000>;
+               interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
+               clock-names = "hclk_host1", "hclk_host1_arb";
+               status = "disabled";
+       };
+
+       gic: interrupt-controller@fee00000 {
+               compatible = "arm,gic-v3";
+               #interrupt-cells = <3>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges;
+               interrupt-controller;
+
+               reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
+                     <0x0 0xfef00000 0 0xc0000>, /* GICR */
+                     <0x0 0xfff00000 0 0x10000>, /* GICC */
+                     <0x0 0xfff10000 0 0x10000>, /* GICH */
+                     <0x0 0xfff20000 0 0x10000>; /* GICV */
+               interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+               its: interrupt-controller@fee20000 {
+                       compatible = "arm,gic-v3-its";
+                       msi-controller;
+                       reg = <0x0 0xfee20000 0x0 0x20000>;
+               };
+       };
+
+       uart0: serial@ff180000 {
+               compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
+               reg = <0x0 0xff180000 0x0 0x100>;
+               clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+               clock-names = "baudclk", "apb_pclk";
+               interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+               reg-shift = <2>;
+               reg-io-width = <4>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+               status = "disabled";
+       };
+
+       uart1: serial@ff190000 {
+               compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
+               reg = <0x0 0xff190000 0x0 0x100>;
+               clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+               clock-names = "baudclk", "apb_pclk";
+               interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+               reg-shift = <2>;
+               reg-io-width = <4>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&uart1_xfer>;
+               status = "disabled";
+       };
+
+       uart2: serial@ff1a0000 {
+               compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
+               reg = <0x0 0xff1a0000 0x0 0x100>;
+               clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+               clock-names = "baudclk", "apb_pclk";
+               interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+               reg-shift = <2>;
+               reg-io-width = <4>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&uart2c_xfer>;
+               status = "disabled";
+       };
+
+       uart3: serial@ff1b0000 {
+               compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
+               reg = <0x0 0xff1b0000 0x0 0x100>;
+               clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+               clock-names = "baudclk", "apb_pclk";
+               interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+               reg-shift = <2>;
+               reg-io-width = <4>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
+               status = "disabled";
+       };
+
+       spi0: spi@ff1c0000 {
+               compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
+               reg = <0x0 0xff1c0000 0x0 0x1000>;
+               clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
+               clock-names = "spiclk", "apb_pclk";
+               interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       spi1: spi@ff1d0000 {
+               compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
+               reg = <0x0 0xff1d0000 0x0 0x1000>;
+               clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
+               clock-names = "spiclk", "apb_pclk";
+               interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       spi2: spi@ff1e0000 {
+               compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
+               reg = <0x0 0xff1e0000 0x0 0x1000>;
+               clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
+               clock-names = "spiclk", "apb_pclk";
+               interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       spi4: spi@ff1f0000 {
+               compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
+               reg = <0x0 0xff1f0000 0x0 0x1000>;
+               clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
+               clock-names = "spiclk", "apb_pclk";
+               interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       spi5: spi@ff200000 {
+               compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
+               reg = <0x0 0xff200000 0x0 0x1000>;
+               clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
+               clock-names = "spiclk", "apb_pclk";
+               interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       pmugrf: syscon@ff320000 {
+               compatible = "rockchip,rk3399-pmugrf", "syscon";
+               reg = <0x0 0xff320000 0x0 0x1000>;
+       };
+
+       spi3: spi@ff350000 {
+               compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
+               reg = <0x0 0xff350000 0x0 0x1000>;
+               clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
+               clock-names = "spiclk", "apb_pclk";
+               interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               status = "disabled";
+       };
+
+       uart4: serial@ff370000 {
+               compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
+               reg = <0x0 0xff370000 0x0 0x100>;
+               clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
+               clock-names = "baudclk", "apb_pclk";
+               interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+               reg-shift = <2>;
+               reg-io-width = <4>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&uart4_xfer>;
+               status = "disabled";
+       };
+
+       pwm0: pwm@ff420000 {
+               compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
+               reg = <0x0 0xff420000 0x0 0x10>;
+               #pwm-cells = <3>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pwm0_pin>;
+               clocks = <&pmucru PCLK_RKPWM_PMU>;
+               clock-names = "pwm";
+               status = "disabled";
+       };
+
+       pwm1: pwm@ff420010 {
+               compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
+               reg = <0x0 0xff420010 0x0 0x10>;
+               #pwm-cells = <3>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pwm1_pin>;
+               clocks = <&pmucru PCLK_RKPWM_PMU>;
+               clock-names = "pwm";
+               status = "disabled";
+       };
+
+       pwm2: pwm@ff420020 {
+               compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
+               reg = <0x0 0xff420020 0x0 0x10>;
+               #pwm-cells = <3>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pwm2_pin>;
+               clocks = <&pmucru PCLK_RKPWM_PMU>;
+               clock-names = "pwm";
+               status = "disabled";
+       };
+
+       pwm3: pwm@ff420030 {
+               compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
+               reg = <0x0 0xff420030 0x0 0x10>;
+               #pwm-cells = <3>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&pwm3a_pin>;
+               clocks = <&pmucru PCLK_RKPWM_PMU>;
+               clock-names = "pwm";
+               status = "disabled";
+       };
+
+       pmucru: pmu-clock-controller@ff750000 {
+               compatible = "rockchip,rk3399-pmucru";
+               reg = <0x0 0xff750000 0x0 0x1000>;
+               #clock-cells = <1>;
+               #reset-cells = <1>;
+               assigned-clocks = <&pmucru PLL_PPLL>;
+               assigned-clock-rates = <676000000>;
+       };
+
+       cru: clock-controller@ff760000 {
+               compatible = "rockchip,rk3399-cru";
+               reg = <0x0 0xff760000 0x0 0x1000>;
+               #clock-cells = <1>;
+               #reset-cells = <1>;
+       };
+
+       grf: syscon@ff770000 {
+               compatible = "rockchip,rk3399-grf", "syscon";
+               reg = <0x0 0xff770000 0x0 0x10000>;
+       };
+
+       watchdog@ff840000 {
+               compatible = "snps,dw-wdt";
+               reg = <0x0 0xff840000 0x0 0x100>;
+               clocks = <&cru PCLK_WDT>;
+               interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+       };
+
+       spdif: spdif@ff870000 {
+               compatible = "rockchip,rk3399-spdif";
+               reg = <0x0 0xff870000 0x0 0x1000>;
+               interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+               dmas = <&dmac_bus 7>;
+               dma-names = "tx";
+               clock-names = "mclk", "hclk";
+               clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&spdif_bus>;
+               status = "disabled";
+       };
+
+       i2s0: i2s@ff880000 {
+               compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
+               reg = <0x0 0xff880000 0x0 0x1000>;
+               rockchip,grf = <&grf>;
+               interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+               dmas = <&dmac_bus 0>, <&dmac_bus 1>;
+               dma-names = "tx", "rx";
+               clock-names = "i2s_clk", "i2s_hclk";
+               clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&i2s0_8ch_bus>;
+               status = "disabled";
+       };
+
+       i2s1: i2s@ff890000 {
+               compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
+               reg = <0x0 0xff890000 0x0 0x1000>;
+               interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+               dmas = <&dmac_bus 2>, <&dmac_bus 3>;
+               dma-names = "tx", "rx";
+               clock-names = "i2s_clk", "i2s_hclk";
+               clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&i2s1_2ch_bus>;
+               status = "disabled";
+       };
+
+       i2s2: i2s@ff8a0000 {
+               compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
+               reg = <0x0 0xff8a0000 0x0 0x1000>;
+               interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+               dmas = <&dmac_bus 4>, <&dmac_bus 5>;
+               dma-names = "tx", "rx";
+               clock-names = "i2s_clk", "i2s_hclk";
+               clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
+               status = "disabled";
+       };
+
+       pinctrl: pinctrl {
+               compatible = "rockchip,rk3399-pinctrl";
+               rockchip,grf = <&grf>;
+               rockchip,pmu = <&pmugrf>;
+               #address-cells = <0x2>;
+               #size-cells = <0x2>;
+               ranges;
+
+               gpio0: gpio0@ff720000 {
+                       compatible = "rockchip,gpio-bank";
+                       reg = <0x0 0xff720000 0x0 0x100>;
+                       clocks = <&pmucru PCLK_GPIO0_PMU>;
+                       interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+
+                       gpio-controller;
+                       #gpio-cells = <0x2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <0x2>;
+               };
+
+               gpio1: gpio1@ff730000 {
+                       compatible = "rockchip,gpio-bank";
+                       reg = <0x0 0xff730000 0x0 0x100>;
+                       clocks = <&pmucru PCLK_GPIO1_PMU>;
+                       interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+
+                       gpio-controller;
+                       #gpio-cells = <0x2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <0x2>;
+               };
+
+               gpio2: gpio2@ff780000 {
+                       compatible = "rockchip,gpio-bank";
+                       reg = <0x0 0xff780000 0x0 0x100>;
+                       clocks = <&cru PCLK_GPIO2>;
+                       interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+
+                       gpio-controller;
+                       #gpio-cells = <0x2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <0x2>;
+               };
+
+               gpio3: gpio3@ff788000 {
+                       compatible = "rockchip,gpio-bank";
+                       reg = <0x0 0xff788000 0x0 0x100>;
+                       clocks = <&cru PCLK_GPIO3>;
+                       interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+
+                       gpio-controller;
+                       #gpio-cells = <0x2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <0x2>;
+               };
+
+               gpio4: gpio4@ff790000 {
+                       compatible = "rockchip,gpio-bank";
+                       reg = <0x0 0xff790000 0x0 0x100>;
+                       clocks = <&cru PCLK_GPIO4>;
+                       interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+
+                       gpio-controller;
+                       #gpio-cells = <0x2>;
+
+                       interrupt-controller;
+                       #interrupt-cells = <0x2>;
+               };
+
+               pcfg_pull_up: pcfg-pull-up {
+                       bias-pull-up;
+               };
+
+               pcfg_pull_down: pcfg-pull-down {
+                       bias-pull-down;
+               };
+
+               pcfg_pull_none: pcfg-pull-none {
+                       bias-disable;
+               };
+
+               pcfg_pull_none_12ma: pcfg-pull-none-12ma {
+                       bias-disable;
+                       drive-strength = <12>;
+               };
+
+               pcfg_pull_up_8ma: pcfg-pull-up-8ma {
+                       bias-pull-up;
+                       drive-strength = <8>;
+               };
+
+               pcfg_pull_down_4ma: pcfg-pull-down-4ma {
+                       bias-pull-down;
+                       drive-strength = <4>;
+               };
+
+               pcfg_pull_up_2ma: pcfg-pull-up-2ma {
+                       bias-pull-up;
+                       drive-strength = <2>;
+               };
+
+               pcfg_pull_down_12ma: pcfg-pull-down-12ma {
+                       bias-pull-down;
+                       drive-strength = <12>;
+               };
+
+               pcfg_pull_none_13ma: pcfg-pull-none-13ma {
+                       bias-disable;
+                       drive-strength = <13>;
+               };
+
+               i2c0 {
+                       i2c0_xfer: i2c0-xfer {
+                               rockchip,pins =
+                                       <1 15 RK_FUNC_2 &pcfg_pull_none>,
+                                       <1 16 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+               };
+
+               i2c1 {
+                       i2c1_xfer: i2c1-xfer {
+                               rockchip,pins =
+                                       <4 2 RK_FUNC_1 &pcfg_pull_none>,
+                                       <4 1 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               i2c2 {
+                       i2c2_xfer: i2c2-xfer {
+                               rockchip,pins =
+                                       <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
+                                       <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
+                       };
+               };
+
+               i2c3 {
+                       i2c3_xfer: i2c3-xfer {
+                               rockchip,pins =
+                                       <4 17 RK_FUNC_1 &pcfg_pull_none>,
+                                       <4 16 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               i2c4 {
+                       i2c4_xfer: i2c4-xfer {
+                               rockchip,pins =
+                                       <1 12 RK_FUNC_1 &pcfg_pull_none>,
+                                       <1 11 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               i2c5 {
+                       i2c5_xfer: i2c5-xfer {
+                               rockchip,pins =
+                                       <3 11 RK_FUNC_2 &pcfg_pull_none>,
+                                       <3 10 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+               };
+
+               i2c6 {
+                       i2c6_xfer: i2c6-xfer {
+                               rockchip,pins =
+                                       <2 10 RK_FUNC_2 &pcfg_pull_none>,
+                                       <2 9 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+               };
+
+               i2c7 {
+                       i2c7_xfer: i2c7-xfer {
+                               rockchip,pins =
+                                       <2 8 RK_FUNC_2 &pcfg_pull_none>,
+                                       <2 7 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+               };
+
+               i2c8 {
+                       i2c8_xfer: i2c8-xfer {
+                               rockchip,pins =
+                                       <1 21 RK_FUNC_1 &pcfg_pull_none>,
+                                       <1 20 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               i2s0 {
+                       i2s0_8ch_bus: i2s0-8ch-bus {
+                               rockchip,pins =
+                                       <3 24 RK_FUNC_1 &pcfg_pull_none>,
+                                       <3 25 RK_FUNC_1 &pcfg_pull_none>,
+                                       <3 26 RK_FUNC_1 &pcfg_pull_none>,
+                                       <3 27 RK_FUNC_1 &pcfg_pull_none>,
+                                       <3 28 RK_FUNC_1 &pcfg_pull_none>,
+                                       <3 29 RK_FUNC_1 &pcfg_pull_none>,
+                                       <3 30 RK_FUNC_1 &pcfg_pull_none>,
+                                       <3 31 RK_FUNC_1 &pcfg_pull_none>,
+                                       <4 0 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               i2s1 {
+                       i2s1_2ch_bus: i2s1-2ch-bus {
+                               rockchip,pins =
+                                       <4 3 RK_FUNC_1 &pcfg_pull_none>,
+                                       <4 4 RK_FUNC_1 &pcfg_pull_none>,
+                                       <4 5 RK_FUNC_1 &pcfg_pull_none>,
+                                       <4 6 RK_FUNC_1 &pcfg_pull_none>,
+                                       <4 7 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               spdif {
+                       spdif_bus: spdif-bus {
+                               rockchip,pins =
+                                       <4 21 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               spi0 {
+                       spi0_clk: spi0-clk {
+                               rockchip,pins =
+                                       <3 6 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi0_cs0: spi0-cs0 {
+                               rockchip,pins =
+                                       <3 7 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi0_cs1: spi0-cs1 {
+                               rockchip,pins =
+                                       <3 8 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi0_tx: spi0-tx {
+                               rockchip,pins =
+                                       <3 5 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi0_rx: spi0-rx {
+                               rockchip,pins =
+                                       <3 4 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+               };
+
+               spi1 {
+                       spi1_clk: spi1-clk {
+                               rockchip,pins =
+                                       <1 9 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi1_cs0: spi1-cs0 {
+                               rockchip,pins =
+                                       <1 10 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi1_rx: spi1-rx {
+                               rockchip,pins =
+                                       <1 7 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi1_tx: spi1-tx {
+                               rockchip,pins =
+                                       <1 8 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+               };
+
+               spi2 {
+                       spi2_clk: spi2-clk {
+                               rockchip,pins =
+                                       <2 11 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+                       spi2_cs0: spi2-cs0 {
+                               rockchip,pins =
+                                       <2 12 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+                       spi2_rx: spi2-rx {
+                               rockchip,pins =
+                                       <2 9 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+                       spi2_tx: spi2-tx {
+                               rockchip,pins =
+                                       <2 10 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+               };
+
+               spi3 {
+                       spi3_clk: spi3-clk {
+                               rockchip,pins =
+                                       <1 17 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+                       spi3_cs0: spi3-cs0 {
+                               rockchip,pins =
+                                       <1 18 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+                       spi3_rx: spi3-rx {
+                               rockchip,pins =
+                                       <1 15 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+                       spi3_tx: spi3-tx {
+                               rockchip,pins =
+                                       <1 16 RK_FUNC_1 &pcfg_pull_up>;
+                       };
+               };
+
+               spi4 {
+                       spi4_clk: spi4-clk {
+                               rockchip,pins =
+                                       <3 2 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi4_cs0: spi4-cs0 {
+                               rockchip,pins =
+                                       <3 3 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi4_rx: spi4-rx {
+                               rockchip,pins =
+                                       <3 0 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi4_tx: spi4-tx {
+                               rockchip,pins =
+                                       <3 1 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+               };
+
+               spi5 {
+                       spi5_clk: spi5-clk {
+                               rockchip,pins =
+                                       <2 22 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi5_cs0: spi5-cs0 {
+                               rockchip,pins =
+                                       <2 23 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi5_rx: spi5-rx {
+                               rockchip,pins =
+                                       <2 20 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+                       spi5_tx: spi5-tx {
+                               rockchip,pins =
+                                       <2 21 RK_FUNC_2 &pcfg_pull_up>;
+                       };
+               };
+
+               uart0 {
+                       uart0_xfer: uart0-xfer {
+                               rockchip,pins =
+                                       <2 16 RK_FUNC_1 &pcfg_pull_up>,
+                                       <2 17 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+
+                       uart0_cts: uart0-cts {
+                               rockchip,pins =
+                                       <2 18 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+
+                       uart0_rts: uart0-rts {
+                               rockchip,pins =
+                                       <2 19 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               uart1 {
+                       uart1_xfer: uart1-xfer {
+                               rockchip,pins =
+                                       <3 12 RK_FUNC_2 &pcfg_pull_up>,
+                                       <3 13 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+               };
+
+               uart2a {
+                       uart2a_xfer: uart2a-xfer {
+                               rockchip,pins =
+                                       <4 8 RK_FUNC_2 &pcfg_pull_up>,
+                                       <4 9 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+               };
+
+               uart2b {
+                       uart2b_xfer: uart2b-xfer {
+                               rockchip,pins =
+                                       <4 16 RK_FUNC_2 &pcfg_pull_up>,
+                                       <4 17 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+               };
+
+               uart2c {
+                       uart2c_xfer: uart2c-xfer {
+                               rockchip,pins =
+                                       <4 19 RK_FUNC_1 &pcfg_pull_up>,
+                                       <4 20 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               uart3 {
+                       uart3_xfer: uart3-xfer {
+                               rockchip,pins =
+                                       <3 14 RK_FUNC_2 &pcfg_pull_up>,
+                                       <3 15 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+
+                       uart3_cts: uart3-cts {
+                               rockchip,pins =
+                                       <3 18 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+
+                       uart3_rts: uart3-rts {
+                               rockchip,pins =
+                                       <3 19 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+               };
+
+               uart4 {
+                       uart4_xfer: uart4-xfer {
+                               rockchip,pins =
+                                       <1 7 RK_FUNC_1 &pcfg_pull_up>,
+                                       <1 8 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               uarthdcp {
+                       uarthdcp_xfer: uarthdcp-xfer {
+                               rockchip,pins =
+                                       <4 21 RK_FUNC_2 &pcfg_pull_up>,
+                                       <4 22 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+               };
+
+               pwm0 {
+                       pwm0_pin: pwm0-pin {
+                               rockchip,pins =
+                                       <4 18 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+
+                       vop0_pwm_pin: vop0-pwm-pin {
+                               rockchip,pins =
+                                       <4 18 RK_FUNC_2 &pcfg_pull_none>;
+                       };
+               };
+
+               pwm1 {
+                       pwm1_pin: pwm1-pin {
+                               rockchip,pins =
+                                       <4 22 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+
+                       vop1_pwm_pin: vop1-pwm-pin {
+                               rockchip,pins =
+                                       <4 18 RK_FUNC_3 &pcfg_pull_none>;
+                       };
+               };
+
+               pwm2 {
+                       pwm2_pin: pwm2-pin {
+                               rockchip,pins =
+                                       <1 19 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               pwm3a {
+                       pwm3a_pin: pwm3a-pin {
+                               rockchip,pins =
+                                       <0 6 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+
+               pwm3b {
+                       pwm3b_pin: pwm3b-pin {
+                               rockchip,pins =
+                                       <1 14 RK_FUNC_1 &pcfg_pull_none>;
+                       };
+               };
+       };
+};
-- 
1.9.1


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