Hello, On Tue, Apr 26, 2016 at 01:15:35PM +0200, Roman Pen wrote: ... > This behaviour can be explained by speculative LOAD of hctx->ctx_map on > CPU#0, which is reordered with clear of PENDING bit and executed _before_ > actual STORE of bit 1 on CPU#1. > > The proper fix is an explicit full barrier <mfence>, which guarantees > that clear of PENDING bit is to be executed before all possible > speculative LOADS or STORES inside actual work function.
Applied to workqueue/for-4.6-fixes. Thanks. -- tejun
