On Wed, Apr 27, 2016 at 10:03:45AM +0200, Ingo Molnar wrote: > * Adam Borowski <kilob...@angband.pl> wrote: > > diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c > > index 86a9bec..5fa1b8e 100644 > > --- a/arch/x86/events/amd/core.c > > +++ b/arch/x86/events/amd/core.c > > @@ -125,6 +125,7 @@ static const u64 amd_perfmon_event_map[] = > > [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c3, > > [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x00d0, /* "Decoder empty" > > event */ > > [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x00d1, /* "Dispatch stalls" > > event */ > > + [PERF_COUNT_HW_REF_CPU_CYCLES] = 0, > > }; > > Hm, I think it would be cleaner and more robust to change this (and all other > similar, if any) arrays to [PERF_COUNT_HW_MAX] instead.
Good idea! Both of Intel's copies (one for p4, one for core+) already set the size this way. -- A tit a day keeps the vet away.
