> There are three different fixes:
> 1. Fix for THRE errata
That should be handled anyway. The current code actually spots this and
uses a backup timer for dodgy UARTS
> 2. Fix for Busy Detect on LCR write
> 3. Workaround for interrupt/data concurrency issue
> case UPIO_MEM:
> +#ifdef CONFIG_PMC_MSP
> + /* Save the LCR value so it can be re-written when a
> + * Busy Detect interrupt occurs. */
> + if (dwapb_offset == UART_LCR)
> + up->dwapb_lcr = value;
> +#endif
> writeb(value, up->port.membase + offset);
> +#ifdef CONFIG_PMC_MSP
> + /* Re-read the IER to ensure any interrupt disabling has
> + * completed before proceeding with ISR. */
> + if (dwapb_offset == UART_IER)
> + value = serial_in(up, dwapb_offset);
> +#endif
> break;
This I would hope you can hide in the platform specific
serial_in/serial_out functions. If you write the UART_LCR save it in
serial_out(), if you read IER etc.
> +#ifdef CONFIG_PMC_MSP
> + } else if ((iir & UART_IER_BUSY) == UART_IER_BUSY) {
> + /*
> + * The MSP (DesignWare APB UART) serial subsystem has a
> + * non-standard interrupt condition (0x7) which means
> + * that the LCR was written while the UART was busy, so
> + * the LCR was not actually written. It is cleared by
> + * reading the special non-standard extended UART status
> + * register.
Ditto... spot this case and whack it in your serial methods.
And we might want to add a void * for board specific insanity to the 8250
structures if we really have to so you can hang your brain damage
privately off that ?
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