From: Borislav Petkov <b...@suse.de> Hi,
this is the second pile of RAS stuff for 4.7. It is mostly AMD F17h enablement and some more work from Tony to divert flow from mcelog and into our new genpool facility. Please queue on tip/ras/core. Thanks. Aravind Gopalakrishnan (3): x86/mce: Log MCEs after a warm rest on AMD, fam 0x17 and later x86/mce: Grade uncorrected errors for SMCA-enabled systems x86/mce: Carve out writes to MCx_STATUS and MCx_CTL Tony Luck (1): x86/mce: Look in genpool instead of mcelog for pending error records Yazen Ghannam (3): x86/mce: Define vendor-specific MSR accessors x86/mce: Detect and use SMCA-specific msr_ops x86/mce: Detect local MCEs properly arch/x86/include/asm/mce.h | 15 +++ arch/x86/kernel/cpu/mcheck/mce-genpool.c | 46 +++++++++ arch/x86/kernel/cpu/mcheck/mce-internal.h | 15 +++ arch/x86/kernel/cpu/mcheck/mce-severity.c | 30 ++++++ arch/x86/kernel/cpu/mcheck/mce.c | 150 ++++++++++++++++++++++-------- arch/x86/kernel/cpu/mcheck/mce_amd.c | 10 +- 6 files changed, 220 insertions(+), 46 deletions(-) -- 2.7.3
