Hello.
Alan wrote:
Ugh, I'm not seeing any *actual* support for MW/SW DMA in this driver...
Thats long been broken. Should be correct in the libata driver
Here's a surprise for you. pata_cmd64x copied the SW/MW DMA setup code
from the IDE driver. No way it could be working. You may check against the
PC64x datasheets (if you have them -- if you don't I think I may share) and
see for yourself -- it's abolutely idiotic.
I.e. MWDMA2 should be working due to the way the driver is written (it
sets up PIO4 timings when auto-tuning DMA) but not the other modes since
speedproc() method is brain-damaged in this part.
Not a suprise to be honest. I fixed some of the ALi stuff when I did it
and I think that was pushed back into drivers/ide. The CMD64x hasn't had
much love really.
Another buglet found by random glancing at this driver:
/**
* cmd648_dma_stop - DMA stop callback
* @qc: Command in progress
*
* DMA has completed.
*/
static void cmd648_bmdma_stop(struct ata_queued_cmd *qc)
{
struct ata_port *ap = qc->ap;
struct pci_dev *pdev = to_pci_dev(ap->host->dev);
u8 dma_intr;
int dma_reg = ap->port_no ? ARTTIM23_INTR_CH1 : CFR_INTR_CH0;
int dma_mask = ap->port_no ? ARTTIM2 : CFR;
ata_bmdma_stop(qc);
pci_read_config_byte(pdev, dma_reg, &dma_intr);
pci_write_config_byte(pdev, dma_reg, dma_intr | dma_mask);
}
dma_reg and dma_mask initializers must have been swapped since ARTTIM2 and
CFR are regster names. So, the code reads/writes semi-random regs...
Wouldn't mind the older 64x (not 640) data sheets if they are sharable.
Sent what I had on this machine. Will looks for newer revision of
PCJ0646U2 spec elsewhere...
MBR, Sergei
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