This series is just for review.
Please do not apply this patch.
Signed-off-by: Masahiro Yamada <[email protected]>
---
drivers/clk/uniphier/Kconfig | 4 ++
drivers/clk/uniphier/Makefile | 1 +
drivers/clk/uniphier/clk-uniphier-sld8.c | 102 +++++++++++++++++++++++++++++++
3 files changed, 107 insertions(+)
create mode 100644 drivers/clk/uniphier/clk-uniphier-sld8.c
diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig
index d789e26..8e930c3 100644
--- a/drivers/clk/uniphier/Kconfig
+++ b/drivers/clk/uniphier/Kconfig
@@ -14,4 +14,8 @@ config CLK_UNIPHIER_PRO4
tristate "Clock driver for UniPhier PH1-Pro4 SoC"
default ARM
+config CLK_UNIPHIER_SLD8
+ tristate "Clock driver for UniPhier PH1-sLD8 SoC"
+ default ARM
+
endif
diff --git a/drivers/clk/uniphier/Makefile b/drivers/clk/uniphier/Makefile
index ceed615..c7a8390 100644
--- a/drivers/clk/uniphier/Makefile
+++ b/drivers/clk/uniphier/Makefile
@@ -6,3 +6,4 @@ obj-y += clk-uniphier-mux.o
obj-$(CONFIG_CLK_UNIPHIER_LD4) += clk-uniphier-ld4.o
obj-$(CONFIG_CLK_UNIPHIER_PRO4) += clk-uniphier-pro4.o
+obj-$(CONFIG_CLK_UNIPHIER_SLD8) += clk-uniphier-sld8.o
diff --git a/drivers/clk/uniphier/clk-uniphier-sld8.c
b/drivers/clk/uniphier/clk-uniphier-sld8.c
new file mode 100644
index 0000000..74574ba
--- /dev/null
+++ b/drivers/clk/uniphier/clk-uniphier-sld8.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2016 Socionext Inc.
+ * Author: Masahiro Yamada <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+
+#include "clk-uniphier.h"
+
+static const struct uniphier_clk_data uniphier_sld8_clk_data[] = {
+ {
+ .name = "spll",
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ .output_index = -1,
+ .data.factor = {
+ .parent_name = "ref",
+ .mult = 64,
+ .div = 1,
+ },
+ },
+ {
+ .name = "upll",
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ .output_index = -1,
+ .data.factor = {
+ .parent_name = "ref",
+ .mult = 288,
+ .div = 25,
+ },
+ },
+ {
+ .name = "uart",
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ .output_index = 0,
+ .data.factor = {
+ .parent_name = "spll",
+ .mult = 1,
+ .div = 20,
+ },
+ },
+ {
+ .name = "i2c",
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ .output_index = 1,
+ .data.factor = {
+ .parent_name = "spll",
+ .mult = 1,
+ .div = 16,
+ },
+ },
+ {
+ .name = "ehci",
+ .type = UNIPHIER_CLK_TYPE_FIXED_FACTOR,
+ .output_index = 5,
+ .data.factor = {
+ .parent_name = "upll",
+ .mult = 1,
+ .div = 12,
+ },
+ },
+ {
+ .name = "stdmac",
+ .type = UNIPHIER_CLK_TYPE_GATE,
+ .output_index = 7,
+ .data.gate = {
+ .parent_name = NULL,
+ .reg = 0x2104,
+ .mask = BIT(10),
+ .enable_val = BIT(10),
+ },
+ },
+ { /* sentinel */ }
+};
+
+static int uniphier_sld8_clk_probe(struct platform_device *pdev)
+{
+ return uniphier_clk_probe(pdev, uniphier_sld8_clk_data);
+}
+
+static struct platform_driver uniphier_sld8_clk_driver = {
+ .probe = uniphier_sld8_clk_probe,
+ .remove = uniphier_clk_remove,
+ .driver = {
+ .name = "uniphier-sld8-clk",
+ },
+};
+module_platform_driver(uniphier_sld8_clk_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <[email protected]>");
+MODULE_DESCRIPTION("UniPhier PH1-sLD8 System Clock Driver");
+MODULE_LICENSE("GPL");
--
1.9.1
