On Wed, May 18, 2016 at 04:10:59PM +0100, David Howells wrote: > (b) An ISYNC instruction is emitted as the Acquire barrier with > __ATOMIC_SEQ_CST, but I'm not sure this is strong enough. > > (c) An LWSYNC instruction is emitted as the Release barrier with > __ATOMIC_ACQ_REL or __ATOMIC_RELEASE. Is this strong enough that > we could use these memorders instead?
Our atomic acquire/release operations are RCpc, so yes. Our locks would like to be RCsc but currently powerpc is an RCpc holdout there as well.
