The Pistachio SoC does not have an IOCU. Hence, DMA is non-coherent. Remove the function checking for iocoherency and select CONFIG_DMA_NONCOHERENT in Kconfig
This code is probably accidentally inherited from Malta. Signed-off-by: Zubair Lutfullah Kakakhel <[email protected]> Reviewed-by: James Hartley <[email protected]> --- arch/mips/Kconfig | 2 +- arch/mips/pistachio/init.c | 25 ------------------------- 2 files changed, 1 insertion(+), 26 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ac91939..266650e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -384,7 +384,7 @@ config MACH_PISTACHIO select CLKSRC_MIPS_GIC select COMMON_CLK select CSRC_R4K - select DMA_MAYBE_COHERENT + select DMA_NONCOHERENT select GPIOLIB select IRQ_MIPS_CPU select LIBFDT diff --git a/arch/mips/pistachio/init.c b/arch/mips/pistachio/init.c index ab79828..387b9df 100644 --- a/arch/mips/pistachio/init.c +++ b/arch/mips/pistachio/init.c @@ -60,29 +60,6 @@ const char *get_system_type(void) return sys_type; } -static void __init plat_setup_iocoherency(void) -{ - /* - * Kernel has been configured with software coherency - * but we might choose to turn it off and use hardware - * coherency instead. - */ - if (mips_cm_numiocu() != 0) { - /* Nothing special needs to be done to enable coherency */ - pr_info("CMP IOCU detected\n"); - hw_coherentio = 1; - if (coherentio == 0) - pr_info("Hardware DMA cache coherency disabled\n"); - else - pr_info("Hardware DMA cache coherency enabled\n"); - } else { - if (coherentio == 1) - pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n"); - else - pr_info("Software DMA cache coherency enabled\n"); - } -} - void __init *plat_get_fdt(void) { if (fw_arg0 != -2) @@ -93,8 +70,6 @@ void __init *plat_get_fdt(void) void __init plat_mem_setup(void) { __dt_setup_arch(plat_get_fdt()); - - plat_setup_iocoherency(); } #define DEFAULT_CPC_BASE_ADDR 0x1bde0000 -- 1.9.1
