On Tue, Jun 07, 2016 at 02:55:52PM +0800, Tan Jui Nee wrote: > From: Andy Shevchenko <andriy.shevche...@linux.intel.com> > > There is already one and at least one more user coming which > require an access to Primary to Sideband bridge (P2SB) in order > to get IO or MMIO bar hidden by BIOS. > Create a driver to access P2SB for x86 devices. > > Signed-off-by: Yong, Jonathan <jonathan.y...@intel.com> > Signed-off-by: Andy Shevchenko <andriy.shevche...@linux.intel.com> > --- > arch/x86/Kconfig | 14 ++++++ > arch/x86/include/asm/p2sb.h | 27 +++++++++++ > arch/x86/platform/intel/Makefile | 1 + > arch/x86/platform/intel/p2sb.c | 99 > ++++++++++++++++++++++++++++++++++++++++ > 4 files changed, 141 insertions(+) > create mode 100644 arch/x86/include/asm/p2sb.h > create mode 100644 arch/x86/platform/intel/p2sb.c > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig > index 2dc18605..589045e 100644 > --- a/arch/x86/Kconfig > +++ b/arch/x86/Kconfig > @@ -606,6 +606,20 @@ config IOSF_MBI_DEBUG > > If you don't require the option or are in doubt, say N. > > +config X86_INTEL_NON_ACPI > + bool "Enable support non-ACPI Intel platforms" > + select PINCTRL > + ---help--- > + Select this option to enables MMIO BAR access over the P2SB for > + non-ACPI Intel SoC platforms. This driver uses the P2SB hide/unhide > + mechanism cooperatively to pass the PCI BAR address to the platform > + driver, currently GPIO on the following SoC products. > + - Apollo Lake
Why do we need Kconfig option for this? I think better is to make P2SB available on CPUs which have one, and that can be detected runtime. If P2SB is not available then p2sb_bar() returns -ENODEV.
