On Mon, Jun 13, 2016 at 01:06:21PM +0200, Peter Zijlstra wrote: > On Wed, Jun 08, 2016 at 11:09:16AM +0200, Heiko Carstens wrote: > > The z13 machine added a fourth level to the cpu topology > > information. The new top level is called drawer. > > > > A drawer contains two books, which used to be the top level. > > > > Adding this additional scheduling domain did show performance > > improvements for some workloads of up to 8%, while there don't > > seem to be any workloads impacted in a negative way. > > Right; so no objection. > > Acked-by: Peter Zijlstra (Intel) <[email protected]>
Thanks! > You still don't want to make NUMA explicit on this thing? So while I > suppose the SC 480M L4 cache does hide some of it, there can be up to 8 > nodes on this thing. Which seems to me there's win to be had by exposing > it. > > Of course, the moment you go all virt/LPAR on it, that all gets really > interesting, but for those cases where you run 1:1 it might make sense. Yes, and actually we are all virt/LPAR always, so this is unfortunately not very easy to do. And yes, I do agree that for the 1:1 case it most likely would make sense, however we don't have any run-time guarantee to stay 1:1. > Also, are you sure you don't want some of the behaviour changed for the > drawer domains? I could for example imagine you wouldn't want > SD_WAKE_AFFINE set (we disable that for NUMA domains as well). That's something we need to look into further as well. Thanks for pointing this out!
