On Mon, Jun 13, 2016 at 04:57:13PM +0200, Sebastian Frias wrote: > Actually we have 128 inputs and 24 outputs, the 24 outputs go straight to the > GIC. > The HW block is a many-to-many router. > There are 128 32bit registers which specify, for each of the corresponding > 128 inputs, to which of the 24 outputs it would be routed to. > > There are 4 32bit registers that can show the RAW status of the 128 inputs, > but they do not latch on the inputs. > That's why our understanding is that on Linux terms it is not an interrupt > controller, but just a many-to-many mux, the only real interrupt-controller > (where one can set if the line is active high or low for example) is the GIC.
Well that does just sound like a mux. But that does mean you either can't use more than 24 inputs at once, or you will be sharing interrupts. I really hate shared interrutps so I would never design something that way, but it is simpler. > Thanks for the background on the i8259 and the cascaded interrupts. > However, our understanding is that it would only be required if more than 24 > devices request IRQ lines, in which case, some of them would have to share a > single GIC IRQ line, right? > Shall we worry about that now? Well if you are sure you never need more than 24 devices registered at once, then it shouldn't be a problem. > This is interesting. > We have one interrupt controller already upstream, > drivers/irqchip/irq-tango.c, and our understanding is that it dispatches one > IRQ at the time, see tangox_dispatch_irqs() function, is that what you are > discussing? That does look like a proper interrupt controller that could be cascaded of another one if needed. -- Len Sorensen
