From: "Victor(Weiguo) Pan" <[email protected]> To get 100% duty cycle (always high), pulse width needs to be set to 256.
Signed-off-by: Victor(Weiguo) Pan <[email protected]> Signed-off-by: Laxman Dewangan <[email protected]> --- drivers/pwm/pwm-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 71b9c4d..575ca8e 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -79,7 +79,7 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, * per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the * nearest integer during division. */ - c = duty_ns * ((1 << PWM_DUTY_WIDTH) - 1) + period_ns / 2; + c = duty_ns * (1 << PWM_DUTY_WIDTH) + period_ns / 2; do_div(c, period_ns); val = (u32)c << PWM_DUTY_SHIFT; -- 2.1.4
