[PATCH v2 08/14] ARM: dts: sun8i: Add thermal sensor node to the sun8i-h3.dtsi

[megous]

From: Ondrej Jirman <meg...@megous.com>

This patch adds nodes for the thermal sensor driver and
the THS clock to the Allwinner sun8i-h3.dtsi file.

Signed-off-by: Ondrej Jirman <meg...@megous.com>
---
 arch/arm/boot/dts/sun8i-h3.dtsi | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index b3247f4..d3c29cc 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -77,6 +77,14 @@
                };
        };
 
+       thermal-zones {
+               cpu_thermal: cpu_thermal {
+                       polling-delay-passive = <330>;
+                       polling-delay = <1000>;
+                       thermal-sensors = <&ths 0>;
+               };
+       };
+
        timer {
                compatible = "arm,armv7-timer";
                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 
IRQ_TYPE_LEVEL_LOW)>,
@@ -239,6 +247,14 @@
                                             "bus_scr", "bus_ephy", "bus_dbg";
                };
 
+               ths_clk: clk@01c20074 {
+                       #clock-cells = <0>;
+                       compatible = "allwinner,sun8i-h3-ths-clk";
+                       reg = <0x01c20074 0x4>;
+                       clocks = <&osc24M>;
+                       clock-output-names = "ths";
+               };
+
                mmc0_clk: clk@01c20088 {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun4i-a10-mmc-clk";
@@ -574,6 +590,18 @@
                        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
                };
 
+               ths: ths@01c25000 {
+                       #thermal-sensor-cells = <0>;
+                       compatible = "allwinner,sun8i-h3-ths";
+                       reg = <0x01c25000 0x400>,
+                             <0x01c14234 0x4>;
+                       interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+                       resets = <&apb1_rst 8>;
+                       reset-names = "ahb";
+                       clocks = <&bus_gates 72>, <&ths_clk>;
+                       clock-names = "ahb", "ths";
+               };
+
                uart0: serial@01c28000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x01c28000 0x400>;
-- 
2.9.0