"Joerg Roedel" <[EMAIL PROTECTED]> writes: > On Tue, Feb 06, 2007 at 12:08:12PM -0700, [EMAIL PROTECTED] wrote: >> "Andreas Herrmann" <[EMAIL PROTECTED]> writes: >> > You are referring to current Linux implementation? >> > The AMD64 architecture increased physical address size in PSE mode to >> > 40 bits. So at least it would be possible to use more than 32 bits. >> >> How do you get 40 physical bits in a 32bit page table entry? My memory >> is that the low bits in the page table entry were well defined and >> accounted for. I'm pretty certain I can account for 6 of the low bits >> off the top of my head. PSE is the page size extension allowing pages >> 2MB/4MB >> pages. > > The access to 40 physical address bits is only possible using large pages > (4MB on 32bit without PAE). In those page tables entrys you only use > bits 22:31 for encoding the physical address. The bits 12:21 are > unused. These unused bits are reused to encode bits 32:39 of the 40 bit > physical address.
Yep. I missed that feature, and I do see it in AMD documentation now that I look. I'm not certain what that would be useful for though. I'm pretty certain doesn't use this feature, we just enable PAE mode. Eric - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
