From: Suravee Suthikulpanit <suravee.suthikulpa...@amd.com>
Introduces a new IOMMU API, amd_iommu_update_ga(), which allows
KVM (SVM) to update existing posted interrupt IOMMU IRTE when
load/unload vcpu.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpa...@amd.com>
---
drivers/iommu/amd_iommu.c | 65 +++++++++++++++++++++++++++++++++++++++++
drivers/iommu/amd_iommu_types.h | 1 +
include/linux/amd-iommu.h | 9 ++++++
3 files changed, 75 insertions(+)
diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c
index fe9b005..4a337dc 100644
--- a/drivers/iommu/amd_iommu.c
+++ b/drivers/iommu/amd_iommu.c
@@ -4461,4 +4461,69 @@ int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
return 0;
}
+
+static int
+update_irte_ga(struct irte_ga *irte, unsigned int devid,
+ u64 base, int cpu, bool is_run)
+{
+ struct irq_remap_table *irt = get_irq_table(devid, false);
+ unsigned long flags;
+
+ if (!irt)
+ return -ENODEV;
+
+ spin_lock_irqsave(&irt->lock, flags);
+
+ if (irte->lo.fields_vapic.guest_mode) {
+ irte->hi.fields.ga_root_ptr = (base >> 12);
+ if (cpu >= 0)
+ irte->lo.fields_vapic.destination = cpu;
+ irte->lo.fields_vapic.is_run = is_run;
+ barrier();
+ }
+
+ spin_unlock_irqrestore(&irt->lock, flags);
+
+ return 0;
+}
+
+int amd_iommu_update_ga(u32 vcpu_id, u32 cpu, u32 vm_id,
+ u64 base, bool is_run)
+{
+ unsigned long flags;
+ struct amd_iommu *iommu;
+
+ if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
+ return 0;
+
+ for_each_iommu(iommu) {
+ struct amd_ir_data *ir_data;
+
+ spin_lock_irqsave(&iommu->gatag_ir_hash_lock, flags);
+
+ /* Note:
+ * We need to update all interrupt remapping table entries
+ * for targeting the specified vcpu. Here, we use gatag
+ * as a hash key and iterate through all entries in the bucket.
+ */
+ hash_for_each_possible(iommu->gatag_ir_hash, ir_data, hnode,
+ AMD_IOMMU_GATAG(vm_id, vcpu_id)) {
+ struct irte_ga *irte = (struct irte_ga *)
ir_data->entry;
+
+ if (!irte->lo.fields_vapic.guest_mode)
+ continue;
+
+ update_irte_ga((struct irte_ga *)ir_data->ref,
+ ir_data->irq_2_irte.devid,
+ base, cpu, is_run);
+ iommu_flush_irt(iommu, ir_data->irq_2_irte.devid);
+ iommu_completion_wait(iommu);
+ }
+
+ spin_unlock_irqrestore(&iommu->gatag_ir_hash_lock, flags);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(amd_iommu_update_ga);
#endif
diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h
index 2ed353b..52160c8 100644
--- a/drivers/iommu/amd_iommu_types.h
+++ b/drivers/iommu/amd_iommu_types.h
@@ -844,6 +844,7 @@ struct amd_ir_data {
union {
struct msi_msg msi_entry;
};
+ void *ref; /* Pointer to the actual irte */
};
#ifdef CONFIG_IRQ_REMAP
diff --git a/include/linux/amd-iommu.h b/include/linux/amd-iommu.h
index 940fdd8..a6fc022 100644
--- a/include/linux/amd-iommu.h
+++ b/include/linux/amd-iommu.h
@@ -179,6 +179,9 @@ static inline int amd_iommu_detect(void) { return -ENODEV; }
/* IOMMU AVIC Function */
extern int amd_iommu_register_ga_log_notifier(int (*notifier)(int, int));
+extern int
+amd_iommu_update_ga(u32 vcpu_id, u32 cpu, u32 vm_id, u64 base, bool is_run);
+
#else /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */
static inline int
@@ -187,6 +190,12 @@ amd_iommu_register_ga_log_notifier(int (*notifier)(int,
int))
return 0;
}
+static inline int
+amd_iommu_update_ga(u32 vcpu_id, u32 cpu, u32 vm_id, u64 base, bool is_run)
+{
+ return 0;
+}
+
#endif /* defined(CONFIG_AMD_IOMMU) && defined(CONFIG_IRQ_REMAP) */
#endif /* _ASM_X86_AMD_IOMMU_H */
--
1.9.1
