On Thu, Feb 08, 2007 at 04:00:03AM -0800, David Miller wrote:
> From: Paul Mackerras <[EMAIL PROTECTED]>
> Date: Thu, 8 Feb 2007 22:10:54 +1100
[]
> Linus and Oleg tried to fix it with various subsequent changes
> to scripts/Kbuild.include, but it's still broken.
And Roland McGrath, but it turned to be very bad.
Maybe you have older set of fixes. I have x86-64 and i386 built,
though with make 3.81(debian).
But it may be ppc specific, as
CFLAGS += $(call cc-option,-mcpu=970)
else
CFLAGS += $(call cc-option,-mcpu=power4)
may be turned to be options without spaces (make V=1)!
> For some reason $(call ...) invocations add spaces. I tried
> another test case:
>
> define test
> $(shell echo -n)
> endef
>
> VAR:=$(call test)
>
> all:
> @echo "\'$(VAR)\'"
>
> And this always prints:
>
> ' TEST'
>
> even with GNU Make version 3.81
>
> If I put a $(strip ...) around the define, the space is
> still there. If I put the $(strip ...) around VAR's
> $(call), the space goes away.
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