- Remove check for parallel PHY
- Set LP-Serial Register Map type
Signed-off-by: Alexandre Bounine <[email protected]>
Cc: Matt Porter <[email protected]>
Cc: Benjamin Herrenschmidt <[email protected]>
Cc: Michael Ellerman <[email protected]>
Cc: Andre van Herk <[email protected]>
Cc: Barry Wood <[email protected]>
Cc: [email protected]
Cc: [email protected]
---
arch/powerpc/sysdev/fsl_rio.c | 12 ++----------
1 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/arch/powerpc/sysdev/fsl_rio.c b/arch/powerpc/sysdev/fsl_rio.c
index 1958838..ee5b9f1 100644
--- a/arch/powerpc/sysdev/fsl_rio.c
+++ b/arch/powerpc/sysdev/fsl_rio.c
@@ -643,19 +643,11 @@ int fsl_rio_setup(struct platform_device *dev)
port->ops = ops;
port->priv = priv;
port->phys_efptr = 0x100;
+ port->phys_rmap = 1;
priv->regs_win = rio_regs_win;
- /* Probe the master port phy type */
ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20);
- port->phy_type = (ccsr & 1) ? RIO_PHY_SERIAL : RIO_PHY_PARALLEL;
- if (port->phy_type == RIO_PHY_PARALLEL) {
- dev_err(&dev->dev, "RIO: Parallel PHY type, unsupported
port type!\n");
- release_resource(&port->iores);
- kfree(priv);
- kfree(port);
- continue;
- }
- dev_info(&dev->dev, "RapidIO PHY type: Serial\n");
+
/* Checking the port training status */
if (in_be32((priv->regs_win + RIO_ESCSR + i*0x20)) & 1) {
dev_err(&dev->dev, "Port %d is not ready. "
--
1.7.8.4
