On 12 July 2016 at 20:02, Fenghua Yu <[email protected]> wrote: > From: Vikas Shivappa <[email protected]> > > On Intel SKUs that support Code Data Prioritization(CDP), intel_rdt > operates in 2 modes - legacy cache allocation mode/default or CDP mode. > > When CDP is enabled, the number of available CLOSids is halved. Hence the > enabling is done when less than half the number of CLOSids available are > used. When CDP is enabled each CLOSid maps to a > data cache mask and an instruction cache mask. The enabling itself is done > by writing to the IA32_PQOS_CFG MSR and can dynamically be enabled or > disabled. > > CDP is disabled when for each (dcache_cbm,icache_cbm) pair, the > dcache_cbm = icache_cbm. > > Signed-off-by: Vikas Shivappa <[email protected]> > Signed-off-by: Fenghua Yu <[email protected]> > Reviewed-by: Tony Luck <[email protected]> > --- > arch/x86/include/asm/intel_rdt.h | 7 +++++ > arch/x86/kernel/cpu/intel_rdt.c | 66 > ++++++++++++++++++++++++++-------------- > 2 files changed, 51 insertions(+), 22 deletions(-) > > diff --git a/arch/x86/include/asm/intel_rdt.h > b/arch/x86/include/asm/intel_rdt.h > index 6e20314..f2cb91d 100644 > --- a/arch/x86/include/asm/intel_rdt.h > +++ b/arch/x86/include/asm/intel_rdt.h > @@ -8,6 +8,7 @@ > #define MAX_CBM_LENGTH 32 > #define IA32_L3_CBM_BASE 0xc90 > #define CBM_FROM_INDEX(x) (IA32_L3_CBM_BASE + x) > +#define MSR_IA32_PQOS_CFG 0xc81 > > extern struct static_key rdt_enable_key; > void __intel_rdt_sched_in(void *dummy); > @@ -17,6 +18,12 @@ struct clos_cbm_table { > unsigned int clos_refcnt; > }; > > +struct clos_config { > + unsigned long *closmap; > + u32 max_closid; > + u32 closids_used; > +}; > +
I think most of this patch is not about CDP, but about moving from an independently defined closmap to one defined as part of struct clos_config. I suggest we combine part of this patch with patch 03/32 and work with struct clos_config right from the beginning. Thanks Nilay
