On Mon, 15 Aug 2016 16:13:14 +0800 Chen-Yu Tsai <w...@csie.org> wrote:
> +/* > + * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from > + * the base (2x, 4x and 8x), and one variable divider (the one true > + * pll audio). > + * > + * We don't have any need for the variable divider for now, so we just > + * hardcode it to match with the clock names > + */ > +#define SUN6I_A31_PLL_AUDIO_REG 0x008 > + > +static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", > + "osc24M", 0x008, > + 8, 7, /* N */ > + 0, 5, /* M */ > + BIT(31), /* gate */ > + BIT(28), /* lock */ > + 0); > + FYI, as in many other SoCs (A83T/H3/..), the multipliers/dividers from the base clock (24MHz) do not give an exact rate for standard audio (44.1kHz and 48kHz). Sigma-Delta Modulation must be used. -- Ken ar c'hentañ | ** Breizh ha Linux atav! ** Jef | http://moinejf.free.fr/
