The irq affinity is required for pmu interrupts.

Signed-off-by: Lars Persson <lar...@axis.com>
---
 arch/arm/boot/dts/artpec6.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/boot/dts/artpec6.dtsi b/arch/arm/boot/dts/artpec6.dtsi
index 4e40d55..3489019c 100644
--- a/arch/arm/boot/dts/artpec6.dtsi
+++ b/arch/arm/boot/dts/artpec6.dtsi
@@ -150,6 +150,7 @@
                compatible = "arm,cortex-a9-pmu";
                interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
                        <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&cpu0>, <&cpu1>;
                interrupt-parent = <&intc>;
        };
 
-- 
2.1.4

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