[PATCH v2 15/15] Move msleeps to address Guenter's comments.

[Bjorn Helgaas]

---
 drivers/pci/host/pcie-rockchip.c |   35 +++++++----------------------------
 1 file changed, 7 insertions(+), 28 deletions(-)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index e33d2f7..d293a62 100644
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -481,24 +481,12 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
                        break;
                }
 
-               msleep(20);
-
-               if (!time_before(jiffies, timeout)) {
-                       err = -ETIMEDOUT;
-                       break;
-               }
-       }
-
-       /* Double check gen1 training */
-       if (err) {
-               status = rockchip_pcie_read(rockchip,
-                                           PCIE_CLIENT_BASIC_STATUS1);
-               err = ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
-                      PCIE_CLIENT_LINK_STATUS_UP) ? 0 : -ETIMEDOUT;
-               if (err) {
+               if (time_after(jiffies, timeout)) {
                        dev_err(dev, "PCIe link training gen1 timeout!\n");
-                       return err;
+                       return -ETIMEDOUT;
                }
+
+               msleep(20);
        }
 
        /*
@@ -518,21 +506,12 @@ static int rockchip_pcie_init_port(struct rockchip_pcie 
*rockchip)
                        break;
                }
 
-               msleep(20);
-
-               if (!time_before(jiffies, timeout)) {
-                       err = -ETIMEDOUT;
+               if (time_after(jiffies, timeout)) {
+                       dev_dbg(dev, "PCIe link training gen2 timeout, fall 
back to gen1!\n");
                        break;
                }
-       }
 
-       /* Double check gen2 training */
-       if (err) {
-               status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
-               err = ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
-                      PCIE_CORE_PL_CONF_SPEED_5G) ? 0 : -ETIMEDOUT;
-               if (err)
-                       dev_dbg(dev, "PCIe link training gen2 timeout, fall 
back to gen1!\n");
+               msleep(20);
        }
 
        /* Check the final link width from negotiated lane counter from MGMT */