On Tue, Aug 30, 2016 at 9:54 AM, Andrew Jeffery <[email protected]> wrote:
> From: Joel Stanley <[email protected]> > > The Aspeed SoCs contain GPIOs banked by letter, where each bank contains > 8 pins. The GPIO banks are then grouped in sets of four in the register > layout. > > The implementation exposes multiple banks through the one driver and > requests and releases pins via the pinctrl subsystem. The hardware > supports generation of interrupts from all GPIO-capable pins. > > A number of hardware features are not yet supported: Configuration of > interrupt direction (ARM or LPC), debouncing, and WDT reset tolerance > for output ports. > > Signed-off-by: Joel Stanley <[email protected]> > Signed-off-by: Alistair Popple <[email protected]> > Signed-off-by: Jeremy Kerr <[email protected]> > Signed-off-by: Andrew Jeffery <[email protected]> Patch applied to the GPIO tree. As there are no compile-time dependencies between the pin control and GPIO drivers I choose to merge the pinctrl stuff through the pinctrl tree and the GPIO stuff through the GPIO tree. Yours, Linus Walleij
