Hi Keith,

[auto build test ERROR on pci/next]
[also build test ERROR on v4.8-rc6 next-20160913]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for 
convenience) to record what (public, well-known) commit your patch series was 
built on]
[Check https://git-scm.com/docs/git-format-patch for more information]

url:    
https://github.com/0day-ci/linux/commits/Keith-Busch/pciehp-Let-user-control-LED-status/20160913-231123
base:   https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: x86_64-randconfig-x010-201637 (attached as .config)
compiler: gcc-6 (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All errors (new ones prefixed by >>):

   drivers/pci/hotplug/pciehp_hpc.c: In function 
'pciehp_get_raw_attention_status':
>> drivers/pci/hotplug/pciehp_hpc.c:366:3: error: 'status' undeclared (first 
>> use in this function)
     *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC)) >> 6;
      ^~~~~~
   drivers/pci/hotplug/pciehp_hpc.c:366:3: note: each undeclared identifier is 
reported only once for each function it appears in
   drivers/pci/hotplug/pciehp_hpc.c: In function 
'pciehp_set_raw_attention_status':
>> drivers/pci/hotplug/pciehp_hpc.c:452:30: error: 'value' undeclared (first 
>> use in this function)
     pcie_write_cmd_nowait(ctrl, value << 6,
                                 ^~~~~

vim +/status +366 drivers/pci/hotplug/pciehp_hpc.c

   360  {
   361          struct slot *slot = hotplug_slot->private;
   362          struct pci_dev *pdev = ctrl_dev(slot->ctrl);
   363          u16 slot_ctrl;
   364  
   365          pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
 > 366          *status = (slot_ctrl & (PCI_EXP_SLTCTL_AIC | 
 > PCI_EXP_SLTCTL_PIC)) >> 6;
   367          return 0;
   368  }
   369  
   370  void pciehp_get_attention_status(struct slot *slot, u8 *status)
   371  {
   372          struct controller *ctrl = slot->ctrl;
   373          struct pci_dev *pdev = ctrl_dev(ctrl);
   374          u16 slot_ctrl;
   375  
   376          pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
   377          ctrl_dbg(ctrl, "%s: SLOTCTRL %x, value read %x\n", __func__,
   378                   pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 
slot_ctrl);
   379  
   380          switch (slot_ctrl & PCI_EXP_SLTCTL_AIC) {
   381          case PCI_EXP_SLTCTL_ATTN_IND_ON:
   382                  *status = 1;    /* On */
   383                  break;
   384          case PCI_EXP_SLTCTL_ATTN_IND_BLINK:
   385                  *status = 2;    /* Blink */
   386                  break;
   387          case PCI_EXP_SLTCTL_ATTN_IND_OFF:
   388                  *status = 0;    /* Off */
   389                  break;
   390          default:
   391                  *status = 0xFF;
   392                  break;
   393          }
   394  }
   395  
   396  void pciehp_get_power_status(struct slot *slot, u8 *status)
   397  {
   398          struct controller *ctrl = slot->ctrl;
   399          struct pci_dev *pdev = ctrl_dev(ctrl);
   400          u16 slot_ctrl;
   401  
   402          pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &slot_ctrl);
   403          ctrl_dbg(ctrl, "%s: SLOTCTRL %x value read %x\n", __func__,
   404                   pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 
slot_ctrl);
   405  
   406          switch (slot_ctrl & PCI_EXP_SLTCTL_PCC) {
   407          case PCI_EXP_SLTCTL_PWR_ON:
   408                  *status = 1;    /* On */
   409                  break;
   410          case PCI_EXP_SLTCTL_PWR_OFF:
   411                  *status = 0;    /* Off */
   412                  break;
   413          default:
   414                  *status = 0xFF;
   415                  break;
   416          }
   417  }
   418  
   419  void pciehp_get_latch_status(struct slot *slot, u8 *status)
   420  {
   421          struct pci_dev *pdev = ctrl_dev(slot->ctrl);
   422          u16 slot_status;
   423  
   424          pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
   425          *status = !!(slot_status & PCI_EXP_SLTSTA_MRLSS);
   426  }
   427  
   428  void pciehp_get_adapter_status(struct slot *slot, u8 *status)
   429  {
   430          struct pci_dev *pdev = ctrl_dev(slot->ctrl);
   431          u16 slot_status;
   432  
   433          pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
   434          *status = !!(slot_status & PCI_EXP_SLTSTA_PDS);
   435  }
   436  
   437  int pciehp_query_power_fault(struct slot *slot)
   438  {
   439          struct pci_dev *pdev = ctrl_dev(slot->ctrl);
   440          u16 slot_status;
   441  
   442          pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
   443          return !!(slot_status & PCI_EXP_SLTSTA_PFD);
   444  }
   445  
   446  int pciehp_set_raw_attention_status(struct hotplug_slot *hotplug_slot,
   447                                                                  u8 
status)
   448  {
   449          struct slot *slot = hotplug_slot->private;
   450          struct controller *ctrl = slot->ctrl;
   451  
 > 452          pcie_write_cmd_nowait(ctrl, value << 6,
   453                                PCI_EXP_SLTCTL_AIC | PCI_EXP_SLTCTL_PIC);
   454          return 0;
   455  }

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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