Hi Ben, >> >> ------------------ >> >> >> >> [ Upstream commit 1382ea631ddddb634850a3795527db0feeff5aaf ] >> >> >> >> The X-Gene clock driver missed the divider shift operation when >> >> set the divider value. >> >> >> >> Signed-off-by: Loc Ho <l...@apm.com> >> >> Fixes: 308964caeebc ("clk: Add APM X-Gene SoC clock driver") >> >> Signed-off-by: Stephen Boyd <sb...@codeaurora.org> >> >> Signed-off-by: Sasha Levin <alexander.le...@verizon.com> >> >> Signed-off-by: Greg Kroah-Hartman <gre...@linuxfoundation.org> >> >> --- >> >> drivers/clk/clk-xgene.c | 3 ++- >> >> 1 file changed, 2 insertions(+), 1 deletion(-) >> >> >> >> --- a/drivers/clk/clk-xgene.c >> >> +++ b/drivers/clk/clk-xgene.c >> >> @@ -351,7 +351,8 @@ static int xgene_clk_set_rate(struct clk >> >> /* Set new divider */ >> >> data = xgene_clk_read(pclk->param.divider_reg + >> >> pclk->param.reg_divider_offset); >> >> - data &= ~((1 << pclk->param.reg_divider_width) - 1); >> >> + data &= ~((1 << pclk->param.reg_divider_width) - 1) >> >> + << pclk->param.reg_divider_shift; >> > [...] >> > >> > This still does the wrong thing when the shift value is non-zero: it >> > clears all bits to the right of the divider field in data. I think the >> > correct assignment is: >> > >> > data &= ~(((1 << pclk->param.reg_divider_width) - 1) >> > << pclk->param.reg_divider_shift); >> > >> >> Yes... There was an later patch that address this - >> https://patchwork.kernel.org/patch/8458361 > > But it didn't go into this stable update, because you didn't point that > out during review.
Sorry about this. I will keep this in mind in the future. -Loc