On Thu, Sep 29, 2016 at 12:18:58PM -0700, Paul E. McKenney wrote:
> On Thu, Sep 29, 2016 at 08:44:39PM +0200, Peter Zijlstra wrote:
> > On Thu, Sep 29, 2016 at 11:10:15AM -0700, Paul E. McKenney wrote:
> > > > >
> > > > > P0(int *x, int *y)
> > > > > {
> > > > > WRITE_ONCE(*x, 1);
> > > > > smp_wmb();
> > > > > smp_store_release(y, 1);
> > > > > }
> > > > >
> > > > > P1(int *y)
> > > > > {
> > > > > WRITE_ONCE(*y, 2);
> > > > > }
> > > > >
> > > > > P2(int *x, int *y)
> > > > > {
> > > > > r1 = smp_load_acquire(y);
> > > > > r2 = READ_ONCE(*x);
> > > > > }
> > > > >
> > > > > Both ARM and powerpc allow the "after the dust settles" outcome (r1=2
> > > > > &&
> > > > > r2=0), as does the current version of the early prototype Linux-kernel
> > > >
> > > > And the above needs to be (r1!=2 || r2 != 0)... Sigh!
> > >
> > > Make that (y==2 && r1==2 && r2 == 0).
> > >
> > > Any further bids? ;-)
> >
> > Isn't that the trivial P1,P2,P0 order again?
>
> I don't believe so. Wouldn't the final P0 would leave y==1?
Ah, indeed. I was forgetting to 'execute' P0 entirely.
