[PATCH v4 2/4] x86/phi: Add enabling of the R3MWAIT during boot

[Grzegorz Andrejczuk]

If processor is Intel Xeon Phi we enable user-level mwait feature.
Enabling this feature suppreses invalid-opcode error, when MONITOR/MWAIT
is called from ring 3.

Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejc...@intel.com>
---
 Documentation/kernel-parameters.txt |  5 +++++
 arch/x86/kernel/cpu/intel.c         | 35 +++++++++++++++++++++++++++++++++++
 2 files changed, 40 insertions(+)

diff --git a/Documentation/kernel-parameters.txt 
b/Documentation/kernel-parameters.txt
index a4f4d69..d58915b 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -3120,6 +3120,11 @@ bytes respectively. Such letter suffixes can also be 
entirely omitted.
        pg.             [PARIDE]
                        See Documentation/blockdev/paride.txt.
 
+       phir3mwait=     [X86] Disable Intel Xeon Phi x200 ring 3 MONITOR/MWAIT
+                       feature for all cpus.
+                       Format: { disable }
+                       See arch/x86/kernel/cpu/intel.c
+
        pirq=           [SMP,APIC] Manual mp-table setup
                        See Documentation/x86/i386/IO-APIC.txt.
 
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index fcd484d..1134dca 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -61,6 +61,39 @@ void check_mpx_erratum(struct cpuinfo_x86 *c)
        }
 }
 
+#ifdef CONFIG_X86_64
+static int phi_r3mwait_disabled __read_mostly;
+
+static int __init phir3mwait_disable(char *__unused)
+{
+       phi_r3mwait_disabled = 1;
+       pr_warn("x86/phir3mwait: Disabled ring 3 MWAIT for Xeon Phi");
+       return 1;
+}
+__setup("phir3mwait=disable", phir3mwait_disable);
+
+static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
+{
+       if (phi_r3mwait_disabled)
+               return;
+
+       /*
+       * Setting ring 3 MONITOR/MWAIT for thread
+       * when CPU is Xeon Phi Family x200.
+       */
+       if (c->x86 == 6 && c->x86_model == INTEL_FAM6_XEON_PHI_KNL) {
+               u64 msr;
+
+               rdmsrl(MSR_PHI_MISC_THD_FEATURE, msr);
+               msr |= MSR_PHI_MISC_THD_FEATURE_R3MWAIT;
+               wrmsrl(MSR_PHI_MISC_THD_FEATURE, msr);
+       }
+}
+
+#else
+static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *__unused) {}
+#endif
+
 static void early_init_intel(struct cpuinfo_x86 *c)
 {
        u64 misc_enable;
@@ -565,6 +598,8 @@ static void init_intel(struct cpuinfo_x86 *c)
                detect_vmx_virtcap(c);
 
        init_intel_energy_perf(c);
+
+       probe_xeon_phi_r3mwait(c);
 }
 
 #ifdef CONFIG_X86_32
-- 
2.5.1