On Thu, Oct 20, 2016 at 09:37:50PM +0200, Thomas Gleixner wrote: > Well, we have the same issue on other platforms/models which set the > reliable flag.
I was not aware we had other platforms doing this, git grep tells me intel-mid does this as well.. > So one sanity check we can do is to read the IA32_TSC_ADJUST MSR on all > cores. They should all have the same value (usually 0) or at least have a > very minimal delta. If that's off by more than 1us then something is fishy > especially on single socket systems. We could at least WARN about it. > > We could do this in idle occasionally as well, so we can detect the dreaded > "SMI wants to hide the cycles" crapola. Indeed, that sounds like the best we can; and probably should; do.
