On 10/19, Rajendra Nayak wrote: > We seem to have a few branch clocks within gcc for msm8996 which do > have a valid halt bit but can't be used to check branch enable/disable > status as they rely on external clocks in some cases and in some > others only toggle during an ongoing bus transaction. > Mark these with BRANCH_HALT_DELAY, so we just add a delay instead. > > Signed-off-by: Rajendra Nayak <rna...@codeaurora.org> > ---
Srini tells me that if the pcie pipe clocks are enabled after the phy is powered up things work fine and the halt bit checks work. So I don't think we need this patch. Probably the drivers are enabling all their clocks at probe instead of understanding that the phy is outputting a clock that goes into gcc to be gated and then back out into their controller and/or phy. Also, note that these clocks have parents that should be populated by the phys, but so far we haven't done that. That should be fixed as well. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
