Intel Xeon Phi x200 (codenamed Knights Landing) allows to enable MONITOR and MWAIT instructions outside of ring 0.
The feature is controlled by MSR MISC_FEATURE_ENABLES (0x140). Setting bit 1 of this register enables it, so MONITOR and MWAIT instructions do not cause invalid-opcode exceptions when invoked outside of ring 0. The feature MSR is not yet documented in the SDM. Here is the relevant documentation: Hex Dec Name Scope 140H 320 MISC_FEATURE_ENABLES Thread 0 Reserved 1 if set to 1, the MONITOR and MWAIT instructions do not cause invalid-opcode exceptions when executed with CPL > 0 or in virtual-8086 mode. If MWAIT is executed when CPL > 0 or in virtual-8086 mode, and if EAX indicates a C-state other than C0 or C1, the instruction operates as if EAX indicated the C-state C1. 63:2 Reserved Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejc...@intel.com> --- arch/x86/include/asm/msr-index.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 56f4c66..c95da90 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -540,6 +540,11 @@ #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT 39 #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE_BIT) +/* Intel Xeon Phi x200 ring 3 MONITOR/MWAIT */ +#define MSR_MISC_FEATURE_ENABLES 0x00000140 +#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT 1 +#define MSR_MISC_FEATURE_ENABLES_RING3MWAIT (1ULL << MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT) + #define MSR_IA32_TSC_DEADLINE 0x000006E0 /* P4/Xeon+ specific */ -- 2.5.1