Hi Rajendra,
>
>>>
>>> The proper sequence sounds like it should be:
>>>
>>> 1. Enable GDSC for main domain
>>> 2. Enable clocks for main domain (video_{core,maxi,ahb,axi}_clk)
>>> 3. Write the two registers to assert hw signal for subdomains
>>> 4. Enable GDSCs for two subdomains
>>> 5. Enable clocks for subdomains (video_subcore{0,1}_clk)
>>>
>[]..
>
>>
>> So the above is the sequence which is actually carried out on the
>> firmware side. The same can be done in host as well.
>
>By the 'above sequence is done on firmware side', I hope you don;t mean *all*
>5 steps.
>I guess you mean only step 3 is done by firmware?
>
Yes, only step 3.
Regards,
Sricharan
