On Wed, Nov 09, 2016 at 04:51:53PM +0100, Peter Zijlstra wrote:
SNIP
>
> As per a prior mail, the masks on the PMU in question are:
>
> 0x01 - 0001
> 0x03 - 0011
> 0x0e - 1110
> 0x0c - 1100
>
> But since all the masks that have overlap (0xe -> {0xc,0x3}) and (0x3 ->
> 0x1) are of heavier weight, it should all work out I think.
>
> So yes, something like the below (removing the OVERLAP bit) looks like
> its sufficient.
Peter,
could you please take this one?
thanks,
jirka
>
> ---
> arch/x86/events/intel/uncore_snbep.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/events/intel/uncore_snbep.c
> b/arch/x86/events/intel/uncore_snbep.c
> index 272427700d48..e6832be714bc 100644
> --- a/arch/x86/events/intel/uncore_snbep.c
> +++ b/arch/x86/events/intel/uncore_snbep.c
> @@ -669,7 +669,7 @@ static struct event_constraint
> snbep_uncore_cbox_constraints[] = {
> UNCORE_EVENT_CONSTRAINT(0x1c, 0xc),
> UNCORE_EVENT_CONSTRAINT(0x1d, 0xc),
> UNCORE_EVENT_CONSTRAINT(0x1e, 0xc),
> - EVENT_CONSTRAINT_OVERLAP(0x1f, 0xe, 0xff),
> + UNCORE_EVENT_CONSTRAINT(0x1f, 0xe),
> UNCORE_EVENT_CONSTRAINT(0x21, 0x3),
> UNCORE_EVENT_CONSTRAINT(0x23, 0x3),
> UNCORE_EVENT_CONSTRAINT(0x31, 0x3),
